1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to a zone-based optimization framework for performing timing and design rule optimization.
2. Related Art
Conventional circuit optimization techniques force a timing update of the entire design whenever a logic gate is changed. Updating arrival and required times for the entire circuit is computationally expensive. In fact, the worst-case complexity of a full timing update can be exponential with respect to the circuit design's size. As a result, the timing update operation often becomes a runtime bottleneck in conventional synthesis optimization systems (e.g., logic synthesis and physical synthesis).
To combat the runtime bottleneck problem, conventional techniques typically impose a time limit on the optimization process. Although this approach ensures that the optimization process is guaranteed to terminate within the predetermined amount of time, it results in poor QoR.
The problems with conventional approaches—e.g., the long runtimes and the poor QoR—are further exacerbated when a design needs to be optimized for a large number of multi-mode multi-corner (MCMM) scenarios. This is because conventional approaches optimize each scenario independently. In fact, in the MCMM case, conventional techniques often fail to converge on an optimal solution.
Hence, what is needed are efficient circuit optimization techniques which produce good QoR.